The invention relates generally to a method of manufacturing a flash memory device, and more particularly to, a method of manufacturing a flash memory device capable of improving the operation speed and the erase characteristic of a split-type memory cell.
In general, a flash memory cell can be divided into a stack type and a split type depending on what shape a gate electrode has. A method of manufacturing a conventional flash memory device consisted of a flash memory cell having a split type gate electrode will be below explained.
FIGS. 1A to 1G are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device.
FIG. 1A shows a cross-sectional view of a device in which after a gate electrode in which a tunnel oxide film 2, a floating gate 3, a dielectric film 4 and a control gate 5 are stacked is formed on a semiconductor substrate 1, a protection film 6 and a anti-reflection prevention film 7 are then formed on the gate electrode sequentially, wherein the protection film 6 is formed of an oxide film like TEOS and the anti-reflection prevention film 7 is formed of a nitride oxide film.
FIG. 1B shows a cross-sectional view of a device in which after a first photoresist 8 is formed, the first photoresist 8 is patterned to expose a portion of the semiconductor substrate 1 on which a drain region will be formed for forming a drain region having a double doped drain (DDD) structure, and an impurity ion such as phosphorous (P) is then implanted into the exposed portion of the semiconductor substrate 1.
FIG. 1C shows a cross-sectional view of a device in which after the first photoresist 8 removed, a second photoresist 9 is formed on the entire surfaces, the second photoresist 9 is patterned to expose a portion of the semiconductor substrate 1 on which the drain region and a source region will be formed and impurity ions such as arsenic (As) are then implanted into the exposed portion of the semiconductor substrate 1 to form a source region 10A and a drain region 10B. At this time, the drain region 10B has a DDD structure by the impurity ions implantation in FIG. 1B.
FIG. 1D shows a cross-sectional view of a device in which after the second photoresist 9 is removed, an oxide film 11 is formed on the sidewalls of the floating gate 3 and the control gate 5 and on the surface of the semiconductor substrate 1 by oxidization process and an insulating film 12 is then formed on the entire surfaces. At this time, the oxide film 11 formed on the surfaces of the source and drain regions 10A and 10B by the implanted ions is thicker than other portions.
FIG. 1E shows a cross-sectional view of a device in which after a third photoresist 13 is formed on the entire surfaces, the third photoresist 13 is patterned so that the photoresist can be remained only on the portion including the drain region 10B and the exposed insulating film 12 is then blanket-etched to form an insulating spacer 12A on the sidewalls of the gate electrode.
FIG. 1F shows a cross-sectional view of a device in which after the oxide film 11 remained on the surface of the semiconductor substrate 1 and the third photoresist 13 are sequentially removed, a select gate oxide film 14 is formed on the exposed semiconductor substrate 1.
FIG. 1G show a cross-sectional view of a device taken along line A1-A2 in FIG. 2, in which polysilicon and tungsten silicide are sequentially deposited on the entire surfaces to form a select gate consisted of a polysilicon layer 15 and a tungsten silicide layer 16.
In FIG. 2, a reference numeral 40 indicates a mask for forming a device isolation film and a reference numeral 41 indicates a mask for patterning a polysilicon layer for forming a floating gate.
However, the above-mentioned conventional method has the following problems.
Firstly, in the above processes, during a mask process for forming the insulating film spacer 12A, the third photoresist 13 is remained only on the gate electrode formed on both sides of the drain region 10B and the drain region 10B. Therefore, if the distance between the gate electrodes is about 0.44/2 xcexcm, the space between the gate electrodes will be reduced to 0.15 xcexcm by means of the remained insulating film 12. Thus, during the deposition process for forming the tungsten silicide layer 16, an over-hang phenomenon is generated which causes an insufficient coverage. This phenomenon is severe at the portion in which the insulating film spacer 12A is not formed, thus causing irregular thickness and disconnection of the tungsten silicide layer 16. Also, this defected tungsten silicide layer 16 is disconnected by oxidization during a subsequent thermal process. Therefore, due to these problems, the self-resistance Rs of the select gate (word line) is increased and a time delay by which a select gate bias is not transferred within a desired time (90 nsec in case of 0.6 xcexcm) is thus generated, thus lowering the throughput of a device.
Additionally, if the third photoresist 13 is patterned to expose the drain region 10B, during the etching process for removing the oxide film 11, the etchers such as BOE is penetrated into the bottom of the insulating film spacer, thus causing an under-cut phenomenon. Thus, there is a problem that the exposed floating gate 3 and control gate 5 come in contact with the select gate.
Secondly, the flash memory cell is erased by F-N tunneling method which employs an electric field generated by the difference between the potential applied to the control gate 5 and the potential applied to the drain region 10B. Thus, as the overlapping area of the floating gate 3 and the drain region 10B becomes smaller, a good characteristic can be obtained. In other words, as the overlapping area is smaller, the electric field is increased and the tunneling effect is relatively increased, resulting in a good characteristic. However, as the overlapping area of the conventional memory cell is wide to be 0.145 xcexcm, its erase characteristic is bad. Therefore, it is difficult to reduce the overlapping area by the above-mentioned method.
It is therefore an object of the present invention to provide a method of manufacturing a flash memory device capable of solving the above drawbacks, by forming insulating film spacers on both sidewalls of a gate electrode and then forming a drain region.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention is characterized in that it comprises the steps of forming a gate electrode in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are stacked on a semiconductor substrate and then sequentially forming a protection film and an anti-reflection preventing film on the gate electrode, forming a first mask to expose a portion of the semiconductor substrate in which a source region will be formed and performing ion implantation process, after removing the first mask, forming an insulating film on the entire surfaces to form an oxide film on the sidewalls of the floating gate and the control gate, after forming a second mask on the insulating film, blanket-etching the exposed portion of the insulating film to form insulating spacers on both sidewalls of the gate electrode, after removing the second mask, forming a third mask to expose a portion of the semiconductor substrate on which a drain region will be formed and performing ion implantation process, and after removing the third mask, forming a select gate oxide film on the semiconductor substrate and then forming a select gate on the select gate oxide film.
Also, a method of manufacturing a flash memory device according to another embodiment of the present invention is characterized in that it comprises the steps of forming a gate electrode in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are stacked on a semiconductor substrate and then sequentially forming a protection film and an anti-reflection preventing film on the gate electrode, forming a first mask to expose a portion of the semiconductor substrate in which a source region will be formed and performing ion implantation process, after removing the first mask, performing oxidization process to form an oxide film on the sidewalls of the floating gate and the control gate, forming a second mask to expose a portion of the semiconductor substrate in which a drain region will be formed and then performing ion implantation process, after removing the second mask, performing thermal process to form an insulating film on the entire surfaces, after forming a third mask on the insulating film, etching the insulating film to form insulating film spacers on both sidewalls of the gate electrode, and after removing the third mask, forming a select gate oxide film on the exposed portion of the semiconductor substrate, thus forming a select gate on said select gate oxide film.